DFT Team Leader / Tech Lead

Recruitment Consultant

Louis Livingstone

Contact Details

louis@eu-recruit.com +44 (0)333 307 0341

Posted

2 months ago

We’re seeking a dynamic and experienced DFT Team Leader / Technical Leader to join a growing team. In this leadership role, you’ll play a pivotal role in defining, implementing, and monitoring DFT activities throughout the entire product lifecycle. You’ll be responsible for managing, motivating, and developing a high-performing DFT team to ensure exceptional product quality.

Responsibilities

Oversee all DFT activities for all circuits, collaborating closely with the R&D Development Director.
Foster the technical expertise of the DFT team, working in partnership with the technical and development director.
Champion a DFT methodology for the design flow, including DFT insertion, static timing analysis, test vector generation, and validation.
Implement Design Rule Checks (DRC) using SPYGLASS in RTL and develop DFT design constraints.
Analyze DFT metrics and propose solutions to optimize yield, test coverage, and test time across various stages (wafer, package, operation).
Collaborate seamlessly with Front-End Design and Back-End Digital teams to ensure minimal impact on circuit performance, power, and area (PPA) during DFT insertion.
Conduct static timing analysis for all test logic at various levels (physical partition and top-level).
Partner with test engineers to provide and validate test patterns on Automated Test Equipment (ATE).
Define the testing strategy for analog components within the design.
Coordinate the production launch for multiple circuits annually.
Safeguard technical objectives, product quality, and development processes.
Ensure proper documentation of all product-related work.
Lead, organize, and actively participate in DFT reviews.
Report progress and challenges to the project team and development director.

Qualifications & Experience

10+ years of experience in DFT, establishing you as a recognized leader in the field.
Proven track record in defining and planning DFT stages on complex circuits exceeding 30 million instances.
Extensive experience with DFT methodologies including Scan/EDT/SSN, Logic BIST, MBIST, ATPG, and Boundary Scan on complex circuits (over 30M instances).
Proficiency in scripting languages like Pearl, TCL, or Python.
Solid understanding of logic synthesis and static timing analysis.
In-depth knowledge of the DFT flow, with experience in Tessent tools (a plus).
Strong grasp of design concepts, simulations, and physical implementation, considering their impact on final product quality.
Excellent written and oral communication skills in English, coupled with strong leadership, team-building, and a positive, proactive attitude.

Industry

Semiconductor

Contract Type

Permanent

Location

France

Work Model

On-Site

Apply for a vacancy

Apply Now

By applying to this role, you acknowledge that we may collect, store, and process your personal data on our systems.

For more information, please refer to our
Privacy Notice

Name

Phone

Location

Message

Upload CV:

Choose file

Formats: Word, PDF (max. size: 20MB)

Subscribe for industry highlights.

Send Application

DFT Team Leader / Tech Lead

Apply Now

Other relevant jobs

SoC Architect

Senior ASIC EDA Workflow Engineer

Electrical Engineer

Field Application Engineer

Software Verification System Team Lead

Microfabrication Technician

Senior CPU/NPU Performance Workload Modeling Technical Expert

System Software Engineer – BSP

Senior EVA/Video Design Verification Engineer

Staff ASIC Design Engineer – RTL & Constraints

Principal ASIC Design Engineer – Processor Sub-System

Business Development / Field Application Engineering Manager

Senior Power Electronics Engineer

GPU Algorithm Engineer

Analog/Mixed-Signal IC design Director

RF Systems Engineer

Silicon Application Engineer

Silicon Validation Engineer

Reliability & Test Technician

GPU Design Verification Engineer

IT On-Site Support Engineer

Optoelectronic High-Speed Design Engineer

IAM Senior Developer

Head of Verification

FPGA Design Engineer

Principal Mixed Signal Engineer

Analog Design Manager

GPU STA Engineer

Analog Mixed Signal Design Engineer

Quality Engineer

CPU Architect – Hardware

Senior Systems Engineer

Field Service Engineer – Italy

GPU CAD Flow Methodology Engineer

Inertial Sensor Expert

Time Series Data Analysis Based on Large Language Model (LLM) Engineer

Technology Planning Engineer

SoC Architect

Electronics Engineer

System Software Engineer – Networking

Sr Verification Engineer

COMPILER ENGINEER FOR RISC-V CORES

CAD Front End Engineer

GPU Digital Design Engineer

Senior Silicon Integration Engineer

Senior Sales Manager Digital Signage (Micro LED display) in Europe.

Digital IC Design Technical Leader

Physical Design Engineer

System Validation Engineer

Board Level Multi-Physical System Engineer

Digital Verification Engineer

GPU Design Verification Team Lead

System SW Engineer

Back-End Technical Leader

Senior Labview Engineer

Digital Verification Engineer

Senior High-Speed Signal Integrity Engineers

Business Process Analyst

Staff / Senior Staff ATE Test Engineer

PCB Designer Engineers

Account Manager

Sr. IC Digital Verification Engineer

Verification Engineer (Contract)

Senior SW Engineer

Principal Photonics Process Integration Expert

Digital IC Design Engineer

CPU/NPU Performance Projection & Simulation Engineer

Board Level Multi-Physical System Engineer

Splunk System Architect

Junior Physical Design Engineer

Hardware Engineer – PIM

Senior Process Engineer – Silicon Integrated Photonics

Sr. Staff Mixed-Signal Design/Verification Engineer

Senior SerDes System Engineer

DFT Team Leader / Tech Lead

Analog Layout Engineer

Validation Engineer