Expert in Formal Methods

Location: Paris or Grenoble, France

This is a unique opportunity to be at the forefront of groundbreaking work in formal verification.

We are looking for two experienced engineers to fill the roles of Principal Engineer and Expert in Formal Verification. The ideal candidates will have deep expertise in formal methods and their application in two key areas:

• Chip design and verification, including the development of EDA tools, and
• System design, modeling, and verification.

Key Responsibilities

• Lead the development and application of formal verification techniques for chip design and EDA tools, as well as system design and verification.
• Collaborate with interdisciplinary teams to integrate formal methods into both chip-level and system-level design processes.
• Research and implement innovative formal verification solutions to enhance efficiency, accuracy, and scalability.
• Provide technical leadership, mentoring junior engineers and driving the strategic development of formal verification tools and methods.
• For Paris-based roles, take on a leadership role in establishing and growing the local team.

Qualifications

• Extensive experience in formal verification, with practical expertise in chip design and verification (including EDA tools) and system design, modeling, and verification.
• Strong industrial background.
• Proficiency in hardware description languages (HDLs), system modeling and verification.
• Advanced knowledge of formal methods, such as model checking, logic synthesis, and symbolic execution.
• A PhD in computer science, formal methods, or a related field.
• Excellent leadership and problem-solving skills, with a collaborative mindset.