ASIC Verification Engineer

Recruitment Consultant

Jamie Coltman

Contact Details

jc@eu-recruit.com +44 (0)333 307 1115

Posted

2 months ago

A fast growing Security focused Semiconductor manufacturer are looking for an experienced ASIC Verification Engineer to join their team in Amsterdam.

As a UVM Verification Engineer, you will play a key role in ensuring the quality and reliability of our cutting-edge products. Leveraging your extensive experience with Universal Verification Methodology (UVM) and verification techniques, you will contribute to the development of robust verification environments and methodologies. You will collaborate closely with cross-functional teams including design, architecture, and software engineering to deliver high-quality solutions that meet or exceed customer expectations.

Responsibilities

Develop and maintain UVM-based verification environments for complex digital designs.
Create comprehensive verification plans and test cases based on design specifications.
Implement and execute test benches to verify functionality, performance, and compliance with specifications.
Debug issues and work closely with design engineers to resolve them in a timely manner.
Drive continuous improvement of verification methodologies, processes, and best practices.
Mentor junior team members and provide technical guidance as needed.
Collaborate with other teams to ensure alignment of verification efforts with project timelines and goals.
Participate in design reviews and contribute to architectural decisions from a verification perspective.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
Minimum of 5 years of experience in ASIC verification.
Development and deployment of large SoCs on emulation platforms
Practical experience of verifying on processor-based system designs
Experience verifying subsystems for PCIe, DDR, UCIe, Ethernet
Knowledge of C/C++ and/or hardware verification languages e.g. (SystemVerilog, SystemC), shell programming/scripting (g. Tcl, Perl, Python etc.)
Experienced in one or more of various verification methodologies – UVM/OVM, formal, emulation
Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation and support
HW/SW Co-simulation/emulation, QEMU

Industry

Semiconductor

Contract Type

Permanent

Location

Netherlands

Work Model

On-Site

Apply for a vacancy

Apply Now

By applying to this role, you acknowledge that we may collect, store, and process your personal data on our systems.

For more information, please refer to our
Privacy Notice

Name

Phone

Location

Message

Upload CV:

Choose file

Formats: Word, PDF (max. size: 20MB)

Subscribe for industry highlights.

Send Application

ASIC Verification Engineer

Apply Now

Other relevant jobs

SoC Architect

Senior ASIC EDA Workflow Engineer

Electrical Engineer

Field Application Engineer

Software Verification System Team Lead

Microfabrication Technician

Senior CPU/NPU Performance Workload Modeling Technical Expert

System Software Engineer – BSP

Senior EVA/Video Design Verification Engineer

Staff ASIC Design Engineer – RTL & Constraints

Principal ASIC Design Engineer – Processor Sub-System

Business Development / Field Application Engineering Manager

Senior Power Electronics Engineer

GPU Algorithm Engineer

Analog/Mixed-Signal IC design Director

RF Systems Engineer

Silicon Application Engineer

Silicon Validation Engineer

Reliability & Test Technician

GPU Design Verification Engineer

IT On-Site Support Engineer

Optoelectronic High-Speed Design Engineer

IAM Senior Developer

Head of Verification

FPGA Design Engineer

Principal Mixed Signal Engineer

Analog Design Manager

GPU STA Engineer

Analog Mixed Signal Design Engineer

Quality Engineer

CPU Architect – Hardware

Senior Systems Engineer

Field Service Engineer – Italy

GPU CAD Flow Methodology Engineer

Inertial Sensor Expert

Time Series Data Analysis Based on Large Language Model (LLM) Engineer

Technology Planning Engineer

SoC Architect

Electronics Engineer

System Software Engineer – Networking

Sr Verification Engineer

COMPILER ENGINEER FOR RISC-V CORES

CAD Front End Engineer

GPU Digital Design Engineer

Senior Silicon Integration Engineer

Senior Sales Manager Digital Signage (Micro LED display) in Europe.

Digital IC Design Technical Leader

Physical Design Engineer

System Validation Engineer

Board Level Multi-Physical System Engineer

Digital Verification Engineer

GPU Design Verification Team Lead

System SW Engineer

Back-End Technical Leader

Senior Labview Engineer

Digital Verification Engineer

Senior High-Speed Signal Integrity Engineers

Business Process Analyst

Staff / Senior Staff ATE Test Engineer

PCB Designer Engineers

Account Manager

Sr. IC Digital Verification Engineer

Verification Engineer (Contract)

Senior SW Engineer

Principal Photonics Process Integration Expert

Digital IC Design Engineer

CPU/NPU Performance Projection & Simulation Engineer

Board Level Multi-Physical System Engineer

Splunk System Architect

Junior Physical Design Engineer

Hardware Engineer – PIM

Senior Process Engineer – Silicon Integrated Photonics

Sr. Staff Mixed-Signal Design/Verification Engineer

Senior SerDes System Engineer

DFT Team Leader / Tech Lead

Analog Layout Engineer

Validation Engineer