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At European Recruitment, our sectors cover a wide range of industries within the field of technology
At European Recruitment, our sectors cover a wide
range of industries within the field of technology
At European Recruitment, our sectors cover a wide
range of industries within the field of technology
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Senior EVA/Video Design Verification Engineer
Senior EVA/Video Design Verification Engineer
Applies knowledge and experience to architect, design, implement, the testbench to verify the structure and performance computer vision IPs
Creates and maintains verification test benches and environments in System Verilog/UVM
Create and leverage advanced testing frameworks to generate and recreate real-world system integration conditions
•
Collaborates with Architecture, Software, Firmware, Design, Modeling, Emulation and Post-silicon validation teams to define and develop test methodology and content
•
Participate in micro-architecture reviews
•
Collect, organize and execute various forms of system level test content including directed testcases, standards compliance test suites, and system level scenarios
•
Build automation for continue integration and testing based on latest IP
•
Help collect and analyze test results using straightforward statistics and data predictions to track benchmarks and identify issues
•
Works with team members to understand and align on narrow scope of feature development and meet targets.
•
Write technical documentation and feature descriptions for straightforward projects under the direction of a supervisor.
•
Experience in system or sub-system level verification
•
Concurrency, Preemption, Stress testing frameworks
•
Testbench Architecture and Implementation
•
Scripting and automation skills (Python, Make, Airflow etc)
•
Embedded FW Development and Debugging
•
Benchmarking and Performance Analysis
•
Formal verification experience is a plus
•
Experience with emulation/prototyping/hybrid build and execution flows (Veloce, Palladium, Zebu, Protium, HAPS, qemu) is a plus
•
Development of synthesizable transactors, monitors, scoreboards for emulation platforms would be a plus
Qualifications:
•
Minimum 3 years of DV experience using uvm/assertion-based verification technologies
•
Experience in verifying complex SOC or SOC subsystems
•
Experience with caches and DDR memory protocol verification
•
Experience with using memory verification VIP’s
•
Exposure with multiple successful tapeouts from conception to post silicon debug
•
Exposure to Formal verification
•
Experience with Power aware simulations.
•
Experience with perf and power verification.
•
Experience with Gate level Simulations
•
Comprehensive knowledge of interconnect protocols such as APB, AHB, AXI, ACE, ACE-Lite, and NoC concepts.
•
Expertise in diverse integration tasks, including VIP Configuration, Register Model, and Design Debug Features.
Skill proficiency: UVM, system verilog, assertion, C++, python, Power Aware simulations, Gate level SimulationsSenior EVA/Video Design Verification Engineer
•
Applies knowledge and experience to architect, design, implement, the testbench to verify the structure and performance computer vision IPs
•
Creates and maintains verification test benches and environments in System Verilog/UVM
•
Create and leverage advanced testing frameworks to generate and recreate real-world system integration conditions
•
Collaborates with Architecture, Software, Firmware, Design, Modeling, Emulation and Post-silicon validation teams to define and develop test methodology and content
•
Participate in micro-architecture reviews
•
Collect, organize and execute various forms of system level test content including directed testcases, standards compliance test suites, and system level scenarios
•
Build automation for continue integration and testing based on latest IP
•
Help collect and analyze test results using straightforward statistics and data predictions to track benchmarks and identify issues
•
Works with team members to understand and align on narrow scope of feature development and meet targets.
•
Write technical documentation and feature descriptions for straightforward projects under the direction of a supervisor.
•
Experience in system or sub-system level verification
•
Concurrency, Preemption, Stress testing frameworks
•
Testbench Architecture and Implementation
•
Scripting and automation skills (Python, Make, Airflow etc)
•
Embedded FW Development and Debugging
•
Benchmarking and Performance Analysis
•
Formal verification experience is a plus
•
Experience with emulation/prototyping/hybrid build and execution flows (Veloce, Palladium, Zebu, Protium, HAPS, qemu) is a plus
•
Development of synthesizable transactors, monitors, scoreboards for emulation platforms would be a plus
Qualifications:
•
Minimum 3 years of DV experience using uvm/assertion-based verification technologies
•
Experience in verifying complex SOC or SOC subsystems
•
Experience with caches and DDR memory protocol verification
•
Experience with using memory verification VIP’s
•
Exposure with multiple successful tapeouts from conception to post silicon debug
•
Exposure to Formal verification
•
Experience with Power aware simulations.
•
Experience with perf and power verification.
•
Experience with Gate level Simulations
•
Comprehensive knowledge of interconnect protocols such as APB, AHB, AXI, ACE, ACE-Lite, and NoC concepts.
•
Expertise in diverse integration tasks, including VIP Configuration, Register Model, and Design Debug Features.
Skill proficiency: UVM, system verilog, assertion, C++, python, Power Aware simulations, Gate level Simulations
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